Post-synthesis leakage power minimization - INFONA

Post-synthesis leakage power minimization

24/03/2010 · Leakage power has grown ..

Ranganathan, CSE, USF)
Thesis Title: A Compiler Based Leakage Reduction Technique by Power-Gating
Functional Units in Embedded Microprocessors
Continued for a doctoral degree.

Leakage power accounts for an increasingly larger portion of total power consumption in deep submicron technologies.

Post-synthesis sleep transistor insertion for leakage power ..

Lenka, “Modeling of forward gate leakage current in MOSHEMT using Trap Assisted Tunneling and Poole-Frenkel Emission,” IEEE Trans on Electron Devices, Vol.

Dual Vth assignment, which is proven to be an effective method of reducing leakage power in the past, is also effective in toda ...

Vijaykumar, "Gated-Vdd: A Circuit Technique to Reduce Leakage in Deepsubmicron Cache Memories," International Symposium on Low Power Electronics and Design, pp.

We demonstrate good run-time and show that 5-35 % savings in leakage power across the benchmark circuits are possible.


CiteSeerX — Post Sign-off Leakage Power Optimization

Pfeiffenberger,"Sleepy Stack Reduction of Leakage Power," Proceeding of the International Workshop on Power and Timing Modeling, Optimization and Simulation, pp.

we introduce our post sign-off leakage power ..

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On leakage power optimization in clock tree networks …

In the paper, based on a statistical timing analysis (SSTA) framework we presented a dual Vth assignment method which can effectively reduce the leakage power even in the presence of large Vth variation.

Post synthesis clock tree leakage power optimization.

Dual Vth assignment, which is proven to be an effective method of reducing leakage power in the past, is also effective in today’s technologies with certain modifications.

Leakage power analysis and reduction during …

In today’s sub-100nm CMOS technologies, leakage current has become an important part of the total power consumption, affecting both yields and lifetime of digital circuits.

Leakage power minimization for the synthesis of ..

Chandramouli Gopalakrishnan (Spring 2000 - Fall 2003)
Dissertation Title: High Level Techniques for Estimation and Optimization
of Leakage Power of VLSI ASICs
First Employment: CADENCE, Noida India.
Currently working for Synopsys Inc, Bangalore, India.