Phase Locked Loop ( PLL )/Frequency Synthesis - Analog Devices
A phase lock loop frequency synthesizer includes a phase rotator in the feedback path of the PLL. The PLL includes a phase detector, a low pass filter, a charge pump, a voltage controlled oscillator ("VCO"), and a feed back path connecting output of the VCO to the phase detector. The feedback path includes a phase rotator connected to the output of the VCO and to an input of a frequency divider. Coarse frequency control is implemented by adjusting the input reference frequency to the phase detector or by adjusting the divider ratio of the frequency divider. Fine frequency control is achieved by increasing or decreasing the rotation speed of the phase rotator. The phase rotator constantly rotates phase of the VCO output, thereby causing a frequency shift at the output of the phase rotator. The rotation speed of the phase rotator is controlled by an accumulator and a digital frequency control word. Any high frequency noise generated by the phase rotator is rejected by the PLL by properly setting the PLL bandwidth so that the noise falls outside the bandwidth of the PLL. Therefore, a low noise synthesized output from the VCO is generated.
Understanding the basics of PLL frequency synthesis
With all of the complexity and demands of your system-on-a-chip project, thelast thing you want is to have to worry whether your PLL is going to workproperly. Unfortunately, most designers are wary of using PLLs, havinglearned hard lessons about PLL problems on their earlier chips. Whethercomposed of digital or analog circuitry, PLLs perform the analog functionsof generating and aligning the phases of clock signals. Like analog blocks,they are susceptible to analog issues such as noise, which is commonplaceand unavoidable in the hostile mixed-signal environment of today's ICs. MostPLLs available today do not respond well to noise and as a result have verypoor jitter performance. They also tend to have narrow ranges of operation(frequency, voltage, etc.) and are generally not very robust to processvariations. The jitter performance results commonly published can also bemisleading since measuring jitter correctly can be challenging. Jitterresults are often obtained in a noise-free environment or by applying thewrong type of noise, which can yield optimistic and misleading jitterresults.
Frequency Range: 208MHz-304MHz
Step size: 8.33kHz
Reference Frequency: 16MHz
PLL RF Output Impedance: 50Ω
PLL RF Output Power: +17dBm ± 0.5dBm
Digital Lock Detect Signal
Fractional N Divider