Parallel Synthesis Reactor Technology - High …
Using simple, inexpensive equipment, we have used solution-phase parallel synthesis to rapidly prepare hundreds of sulfonamide- and urea-containing FKBP inhibitors, resulting in rapid identification of extremely potent compounds in these series.
Parallel Synthesis Reactor with PolyBLOCK
parallel chemistry; combinatorial chemistry; fluorous chemistry; multi‐component reactions; library design; laboratory equipment; DOS; diversity oriented synthesis
N2 - Using simple, inexpensive equipment, we have used solution-phase parallel synthesis to rapidly prepare hundreds of sulfonamide- and urea-containing FKBP inhibitors, resulting in rapid identification of extremely potent compounds in these series.
With greater sophistication of the equipment, ..
VHDL synthesis tools have predefined VHDL based implementations of adders, subtractors, and making the design process easier. Hardware for addition and subtraction can be automatically generated by operator inferencing in the VHDL code. With current VHDL synthesis tools, IEEE Standard Logic 1164 is the most widely used standard. Some portions of the VHDL model would need to be modified if a different VHDL synthesis CAD tool is used. Typically, only small changes are needed in the library and use statements at the beginning of each source code module to convert to a different CAD tool that supports VHDL Synthesis and IEEE Standard Logic 1164. It is possible for students to examine the synthesized schematics and to experiment with different hardware design tradeoffs such as time and area. When running simulations, a timing diagram can be produced and with some CAD tools it is also possible to back annotate the schematics with simulation values to aid in debugging.
Machine language test programs can be hand assembled, assembled using the SPIM assembler, or even produced using the C compiler. This machine language file is then read into the VHDL model's memory with a read command or hardcoded into a VHDL synthesized ROM used to simulate instruction memory. On current generation PCs, the entire synthesis process for the smaller model requires just a few minutes of computer time. Approximately 3,700 gates are used to implement the basic MIPS VHDL model. After student modifications that add new features, the improved pipelined MIPS processor uses approximately 6,000 gates.
In Computer Engineering 3510, Computer Architecture II, students study pipelining techniques, caches, virtual memory, and I/O hardware. In five laboratory assignments, students modify the synthesizable VHDL model to create an improved MIPS RISC processor with pipelining. In the first laboratory assignment, students pipeline the existing MIPS VHDL model. The VHDL model contains separate modules for each of the five MIPS pipeline stages making the student pipelining process much easier. In this assignment, students add the pipeline registers to each stage or module and modify the control unit. A top-level VHDL structural model is used to connect the five stages together. This structure generates two levels of hierarchy in the design. Breaking up the model into different pipeline stages makes the model much easier to understand and to synthesize. The textbook contains detailed block diagrams of the pipelined MIPS processor. Instructions are traced one clock cycle at a time as they move through the pipeline stages and the value of all busses and control signals are shown in a detailed set of diagrams. Short machine language test programs identical to those presented in the course textbook are run in the simulator to verify correct operation. Using the simulation output, a timing diagram with bus values indicated in hexadecimal, students can check the computer's operation against the textbook's diagrams to verify correct operation. On the PC platform, the VHDL gate level timing simulator can execute the MIPS test programs in a few seconds.
Automatic pipeline stalling using a hazard detection unit is added to the pipelined MIPS VHDL model in the second laboratory assignment. The textbook modifies the control unit to detect a data hazard between instructions in the pipeline and to stall or wait a clock cycle. An example data hazard would be an instruction in the pipeline that writes a register that is then read by the instruction that immediately follows it. The pipelined register write occurs after the read operation for the next instruction and the incorrect register data value would be used. This problem is solved by stalling and later by forwarding. These problems are carefully avoided by the MIPS machine language test programs until they are discussed in the textbook and corrected by adding additional hardware.
Forwarding is added between the pipeline stages to reduce the number of stalls in the third laboratory assignment. As outlined in the textbook, two forwarding multiplexers are added to the ALU inputs along with a more complex control unit that selects the appropriate input when it detects a data hazard. In the case of a register data hazard, the new value of the register is supplied to the ALU by the forwarding multiplexer before it is written back to the register file.
Branch flushing is added to the pipelined MIPS VHDL model in the fourth assignment. When a branch is taken several instructions after the branch are already in the pipeline and they must be automatically cleared out of the pipeline or flushed. The control unit and pipeline registers are modified to detect a branch flush operation and to clear the appropriate pipeline registers to avoid executing unwanted instructions already in the pipeline.
Additional features such as a cache, exception handling hardware, or a different branch instruction scheme are added to the pipelined MIPS VHDL mode in the final laboratory assignment. On the MIPS processor exceptions, such as overflow, save the current PC in a special register and jump to a trap address. In each laboratory assignment, complete synthesis of the design to gate level, followed by a full gate level timing simulation is used to execute short machine language test programs.
Many students encounter timing problems present in their VHDL models that cause errors in the VHDL gate level timing simulation. In every case, it was a real timing problem traced back to VHDL coding errors. They were able to detect and diagnose the problem using the simulation, modify the VHDL model, resynthesize, and eliminate the timing problems. Problems included uninitialized values in flip-flops, combinatorial loops, gating signals with the clock, and logic hazards on critical write control lines. These real world problems familiar to most experienced digital designers are not detected by most RTL or VHDL behavioral simulations.
This unit was removed from a production facility
Source files for the VHDL Synthesis model of the MIPS processor core from  are included with this paper. Versions are available for Viewlogic, Alterra, and Synopsys CAD tools. A link is provided at the end of this paper. When required, synthesis and simulation batch files are also included with each version. These files are stored in zip file format, so an unzip utility, such as pkunzip or WinZip is required. Some portions of the VHDL model would need to be modified if a different VHDL synthesis CAD tool is used. Typically, only small changes are needed in the library and use statements at the beginning of each source code module to convert to a different CAD tool that supports VHDL Synthesis and IEEE Standard Logic 1164.